1. Field of the Invention
The present invention is generally directed to semiconductor memories, and more particularly, to the development of memory cells which can be easily integrated with high performance logic technologies.
2. State of the Art
Those skilled in the art appreciate the desirability of embedding memory technology such as dynamic random access memories (DRAMs), static random access memories (SRAMs), read-only memories (ROMs), electrically erasable programmable read-only memories (EEPROMs), and flash EEPROMs into high performance logic technologies. However, at present, only technologies such as SRAM and ROM are straightforward to integrate into high performance logic technologies. Technologies, such as EEPROM and DRAM technologies are highly dedicated to their specific needs, and are very complex, rendering them unsuitable for straightforward, easy integration into high performance logic technologies.
Because of the numerous applications which exist for integrating flash EEPROM technology with high performance complementary metal oxide semiconductor (CMOS) logic devices (e.g., microprocessors), the development of such a technology would be highly desirable. For example, the applications for such an integrated technology include software updates, storing identification codes, system reconfiguration in the field, look-up tables, manufacturing codes, non-volatile data storage, smart cards which use flash embedded memory, prototyping and various programmable logic devices and field programmable gate arrays.
Known process technologies do not lend themselves to easy integration of commodity flash EEPROM cells with logic devices, such as high performance CMOS devices. Given the wide applicability of flash EEPROM technology, it would be desirable to avoid the process incompatibility problems associated with integrating typical cell designs with conventional logic devices. For example, EEPROM technology is typically implemented using one of four basic cell types: (1) the one transistor stacked-gate flash EEPROM cell; (2) the one and one half transistor split-gate flash EEPROM cell; (3) the double-gate two transistor EEPROM cell; and (4) cells which use edges for control or select gates. There have also been proposals regarding flash memory cells which form self-aligned trenches at the edge of a partially formed stack-gate structure. However, each of these technologies suffers drawbacks which inhibits their straightforward, easy integration into high performance logic technologies.
In addition to process compatibility problems, scaling EEPROM technology into the 0.25 .mu.m regime and below, as is used on typical high performance logic processes, has not been realized. Those skilled in the art have suggested that scaling EEPROM devices is subject to physical limits which may inhibit a reduction in cell size (see, for example, "Nonvolatile Semiconductor Memory Technology", by William D. Brown and Joe E. Brewer, IEEE, Press 1998, page 130). Although the one-transistor stacked-gate double poly technology produces resultant cells which are relatively small, the process is quite complex.
FIG. 1A illustrates features of a 0.18 .mu.m state-of-the-art high performance logic process which uses approximately 20 photolithography steps, and some five levels of interconnect. It would be desirable to formulate a flash-EEPROM cell and technology suitable for embedded applications, which requires a minimum perturbation to the high performance logic technology, and which does not compromise logic function performance. The EEPROM cell should be compatible with deep submicron dimensions and technology. Features of conventional high performance logic technology include use of shallow-trench isolation (STI), use of chemical mechanical polish (CMP), values of transistor length L=0.18 to 0.25 .mu.m, salicides (usually Ti-based), gate oxides 45-55 .ANG., V.sub.d =1.8-2.5V, tungsten plugs with Ti/TiN liner, aluminum alloy interconnects with Ti/TiN barrier and TiN ARC, V.sub.T values down to about 1/4 V, silicon nitride spacers for lightly doped drains, and dual-poly gate electrodes (p+ for p-channel and n+ for n-channel). Self-aligned contacts (SAC) or borderless contacts are generally seen in DRAMs and SRAMs at this technology level.
As gate oxide thicknesses and effective source-to-drain diffusion separation lengths (Leff) have scaled downward, transistor performance has been greatly enhanced. For example, with hot electron channel injection (HECI), programming times have been reduced about two orders of magnitude in moving from 1 .mu.m to 0.25 .mu.m technology. See, for example, K. Yoshikawa, et al, "A flash EEPROM cell scaling including tunnel oxide limitations", ESSDERC 1990 Tech. Dig., 1990, pg. 169 via Stephen Keeney, et al, "Complete Transient Simulation of Flash EEPROM Devices", IEEE Tran. on Electron Dev., 39, No. 12, December 1992, pg. 2750.
A programming time of about 10.sup.-5 seconds is possible for commodity flash memories using technologies below 0.5 .mu.m. See, for example, R. Bez, et al, "The channel hot electron programming of a floating gate MOSFET: An analytical study", 12.sup.th Nonvolatile Semiconductor Memory Workshop, Monterey, Calif., August 1992 via Paolo Pavan, et al, "Flash Memory Cells-An Overview", Proc. IEEE, 85, No. 8, August 1997, page 1248. With this speed, the programming of one million bits would require about 10 seconds.
However, the downward scaling of MOSFETs used for high performance logic has been somewhat more aggressive than that of flash EEPROMS. For logic, both voltage levels and gate oxide thicknesses are less, as compared to flash technology. Thus, it would be desirable to further scale down flash EEPROM technology to render it more compatible with high performance logic technology.
In addition, it would be desirable to provide a compact flash EEPROM cell which only requires one level of poly, yet which is free of the over erase problem associated with, for example, multiple poly cells (e.g., two poly stacked-gate flash EEPROM cells). A maximum cell size of about 40 f.sup.2 would be desirable, wherein the parameter f is the minimum feature size. Using 0.25 .mu.m technology, for example, 2 Mbits of flash memory of this cell size would occupy only about 5% (core area only) of a 1 cm.sup.2 chip.
Although single-poly flash EEPROM cells are known, they are relatively large, and are not easily integrated into a high performance technology. For example, a single-poly flash EEPROM cell is disclosed in "An EEPROM for Microprocessor and Custom Logic", by Cuppens, R., IEEE J. of Solid state Circuits, Vol. SC-20, No. 2, April 1985, page 603. This cell, as shown in FIGS. 1B-1C, couples an n+ region in the substrate to a leg of the floating gate. By applying 13V to the n+, via a metal contact, electrons can be drawn from a thin oxide "injector" region "D". However, the cell area is very large (i.e., approximately 140 f.sup.2).
Another single poly EEPROM cell disclosed in U.S. Pat. No. 5,132,239 has a selection transistor and a floating gate which is capacitively coupled to an n+ region. The cell has a thin oxide region for tunneling electrons. The cell is erased by taking the bit line to ground and the control gate high. Electrons flow to the floating gate, turning off a second transistor connected in series to the selection transistor. The cell is programmed by pulsing the bit line high while holding the control gate at ground. Electrons flow from the floating gate lowering the threshold voltage and turning on the second transistor. However, from the cell drawing in the patent, the area is roughly 100 f.sup.2, which is relatively large.
The known single poly cells use a selection transistor (forming a two transistor cell), and thereby free the device of the over erase problem typical of the two-poly single-transistor stacked gate cells. However, known single poly cells both program and erase through the thin tunneling oxide. In addition, these cells have both "injector" and floating gate regions between the source and drain of the selection transistors, which increases the cell area.